Senior Digital Verification Engineer, Crypto & Security

About the role

Lead verification of post-quantum cryptography and security IP, defining verification strategies and building scalable SystemVerilog/UVM environments for IP and subsystem validation. Drive coverage closure and high-confidence sign-off, develop assertions, apply AI and automation to verification workflows, and collaborate with design and architecture teams while mentoring engineers. Requires a BSc or MSc in Electronics or Electrical Engineering and strong hands-on SystemVerilog and UVM experience, including testbench components such as sequences, drivers, monitors, and scoreboards. Candidates should have practical constrained-random and metrics-driven verification experience, SVA skills, a record of closing functional and code coverage, and strong debugging ability; formal verification knowledge is advantageous.